Power metal-oxide-semiconductor field effect transistors (MOSFETs) have frequently been constructed in the configuration shown in FIG. 1, which shows in cross section a portion of a MOSFET which includes a drain region 10, a source region 11 and a gate 12. Drain region 10 and source region 11 are arranged in a vertical configuration and gate 12 is in a groove or trench configuration. Drain region 10 and source region 11 are both formed of heavily doped N material and gate 12 consists of polysilicon. Layered between drain region 10 and source region 11 are a drift region 13, which is made of a lightly doped N material, and a body region 14, which is made of P material. An insulating layer 15 is interposed between gate 12 and the semiconductor materials, and a dielectric region 19 is partially enclosed by gate 12. Insulating layer 15 and dielectric region 19 are typically formed of silicon dioxide. Drain region 10 is connected to a drain contact 16. Source region 11 is connected to a source contact 17 which provides electrical contact between source region 11 and body region 14. Gate 12 is connected to a gate connection pad on the chip in a manner to be described below.
The device shown in FIG. 1 is in an "off" condition when gate 12 is grounded. When a positive voltage is applied to drain terminal 16 so as to reverse-bias the P-N junction between drift region 13 and body region 14, an electric field is set up within drift region 13. It is known in the art that the electric field reaches its maximum strength on the boundary of insulating layer 15 and drift region 13 at or near a corner in the profile of the gate, such as the point designated as 18 in FIG. 1. The concentration of the electric field at point 18 has frequently led to a voltage breakdown there, which can create oxide traps or pin holes in insulating layer 15, and can result in a short-circuit between drift region 13 and gate 12. Whatever the consequence, a voltage breakdown of this kind can permanently damage the device and render it unfit for further use.
Several ways of solving this problem had been proposed in the prior art. For example, the corner of insulating layer 15 at point 18 can be rounded, as shown in FIG. 2. While this tends to reduce the strength of the electric field in this area and renders the device somewhat more resistant to voltage breakdown, the improvement in this regard is not significant.
Another solution proposed in the prior art is to form a well 20 of heavily doped P material, as shown in FIG. 2. The creation of a P-N junction between well 20 and drift region 13, however, has the undesirable effect of creating a junction field effect transistor in the area designated as 21 in FIG. 2. This tends to choke off the current between drain terminal 16 and source terminal 17. In addition, the creation of a well reduces the cell density possible in the device.